Method of forming conductive layers in the trenches or through holes made in an insulating film on a semiconductor substrate

ABSTRACT

Conductive layers are formed in the trenches made in an insulating film in the following manner. First, an amorphous silicon film  26 A is deposited in the trenches  25  made in a silicon oxide film  24.  A photoresist film  30  is then formed on the amorphous silicon film  26 A by means of spin coating. Then, exposure light is applied to the entire surface of the photoresist film  30,  thereby exposing to light those parts of the photoresist film  30  which lie outside the trenches  25.  The other parts of the photoresist film  30,  which lie in the trenches  25  are not exposed to light because the light reaching them is inadequate. Further, the photoresist film  30  is developed thereby removing those parts of the film  30  which lie outside the trenches  25  and which have been exposed to light. Thereafter, those parts of the amorphous silicon film  26 A, which lie outside the trenches  25,  are removed by means of dry etching using, as a mask, the unexposed parts of the photoresist film  30  which remain in the trenches  25.

TECHNICAL FIELD OF THE INVENTION

[0001] The application is a divisional application of U.S. applicationSer. No. 09/610,114 filed on Jun. 30, 2000. The present Inventionrelates to a method of manufacturing a semiconductor integrated circuitdevice. More particularly, the invention relates to a technique, whichis useful and efficient when applied to the process of formingconductive layers in the trenches or through holes made in an insulatingfilm.

BACKGROUND OF THE INVENTION

[0002] The memory cells of a DRAM (Dynamic Random Access Memory) arearranged at the intersections of a plurality of word lines and aplurality of bit lines, which are provided on the major surface of the,semiconductor substrate. Hence, the memory cells are arranged in rowsand columns on the major surface of the semiconductor substrate. Each ofthe memory cells comprises a MISFET (Metal Insulator Semiconductor FieldEffect Transistor) and a capacitive element. The MISFET is turned on toselect the memory cell. The capacitive element Is connected to theMISFET in series, for storing data.

[0003] Each MISFET for selecting one memory cell is provided in anactive region of the substrate, which is surrounded by element-Isolatingregions. The cell-selecting MISFET comprises a gate insulating film, agate electrode formed integral with a word line, and a pair ofsemiconductor regions serving as the source and the drain, respectively.Each bit line is provided above two adjacent cell-selecting MISFETs andelectrically connected to the common source or drain of the adjacentMISFETs, which are arranged along the bit line. The data-storingcapacitive element is also located above the MISFETs, too, andelectrically connected to the common source or drain of the MISFETs.

[0004] Japanese Patent Application Laid-Open Publication No. 7-7084discloses a DRAM of a stacked capacitor structure, in which data-storingcapacitive elements are provided above cell-selecting MISFETs. In theDRAM disclosed in the publication, the lower electrode (data-storingelectrode) of each data-storing capacitive element is shaped as a hollowcylinder with a larger surface to compensate for the decrease in storedcharge which inevitably results from the size reduction of the memorycell. The upper electrode (plate electrode) of the data-storingcapacitive element is provided above the lower electrode.

[0005] Japanese Patent Application Laid-Open Publication No. 11-17144discloses the technique of forming a reinforcing member made ofinsulating film, on the bottom of a hollow cylindrical lower electrodeof the type described above. The reinforcing member increases themechanical strength of the lower electrode thereby preventing the lowerelectrode from toppling in the course of manufacturing the data-storingcapacitive element.

SUMMARY OF THE INVENTION

[0006] The Inventors of the present invention have been developing thetechnique of first forming a trench in a thick silicon oxide filmdeposited and located above a bit line and then forming the lowerelectrode (data-storing electrode) of a data-storing capacitive elementin the trench.

[0007] The data-storing capacitive element is manufactured as follows.First, a thick silicon oxide film is formed above the bit line. A trenchis made In the silicon oxide film by means of dry etching using a maskmade of a photoresist film. Then, a polycrystalline silicon film isdeposited in the trench and on the silicon oxide film. Thereafter, acoating is formed on the polycrystalline silicon film by means of SOG(Spin On Glass) or the like, thereby protecting the polycrystallinesilicon film. A part of the polycrystalline silicon film, which isprovided on the silicon oxide film, is removed by dry etching. The otherpart of the polycrystalline silicon film, which remains. In the trench,will be used as the lower electrode.

[0008] Next, the SOG film Is removed from the polycrystalline siliconfilm remaining In the trench. The SOG film is removed by dry etching orwet etching based upon the difference In etching rate between thesilicon oxide film and the SOG film.

[0009] Then, a dielectric film, such as a tantalum oxide (Ta205) film,is deposited on the polycrystalline silicon film. A conductive film madeof titanium oxide or the like is deposited on the tantalum oxide film. Adata-storing capacitive element is thereby manufactured, which comprisesa lower electrode made of a polycrystalline silicon film, a capacitanceinsulating film made of a tantalum oxide film, and an upper electrodemade of a titanium oxide film.

[0010] The data-storing capacitive element described above has its lowerelectrode provided in a trench made in a silicon oxide film. Provided inthe trench, the lower electrode would not be toppled as the conventionallower electrode that is shaped like a hollow cylinder, in the course ofmanufacturing the data-storing capacitive element. In view of this, thelower electrode is advantageous over the conventional one. However, thelower electrode of the data-storing capacitive element has a smallersurface than the conventional lower electrode, whose inner surface andouter surface are used as a region to effectively hold the accumulatedcharge. In order to hold the charge reliably, some measures must betaken to increase the surface area of the lower electrode. To Increasethe surface area of the lower electrode, the trench in which the lowerelectrode is provided may be made deeper, and depressions andprojections may be made at the surface of the lower electrode.

[0011] However, the method of manufacturing the lower electrode, whereinthe selective etching of the SOG film Is achieved based upon thedifference in etching rate between the silicon oxide film and the SOGfilm, is disadvantageous In one respect. Since the difference in etchingrate between these films is not sufficiently large, the oxide siliconfilm outside the trench is etched to some extent when the SOG filmcovering the polycrystalline silicon film provided In the trench isetched. Consequently, the upper surface of the silicon oxide filmlowers, in particular where depressions and projections are made at thesurface of the polycrystalline silicon film and over-etching isperformed to remove those parts of the SOG film which remain in thedepressions and between the projections.

[0012] If the upper surface of the silicon oxide film lowers, the upperedge of the polycrystalline silicon film formed in the trench protrudesfrom the plane in which the trench opens. This impairs the surfacesmoothness of the data-storing capacitive element such that it isinevitably impaired. Further, an electric field concentrates at theupper edge of the polycrystalline silicon film, which inevitablyincreases the leakage current of the data-storing capacitive element.

[0013] An object of the present invention is to provide a technique forenhancing the manufacturing yield of a DRAM comprising data-storingcapacitive elements, each having a lower electrode provided in a trenchmade in an insulating film.

[0014] Another object of the invention is to provide a technique offorming a conductive layer in a trench or a through hole made in aninsulating film.

[0015] Additional objects and novel features of the invention will beobvious from the description, which follows, and the drawingsaccompanying the present specification.

[0016] The representative embodiments of this invention are brieflydescribed as follows.

[0017] (1) A method of manufacturing a semiconductor integrated circuitdevice, according to this invention, comprises the following steps:

[0018] (a) forming a first conductive film on a surface of asemiconductor substrate, forming a first insulating film on the firstconductive film, and making a trench or a through hole in the firstinsulating film;

[0019] (b) forming a second conductive film in the trench or the throughhole and on the first insulating film, said second conductive filmextending through the trench or the through hole and electricallyconnected to the first conductive film;

[0020] (c) covering the second conductive film with a photoresist filmand applying exposure light to the photoresist film, thereby exposing tolight at least that part of the photoresist film which lies outside thetrench or the through hole;

[0021] (d) removing a part of the photoresist film which is exposed tolight, thereby leaving the other, unexposed part of the photoresist filmin the trench or the through hole; and

[0022] (e) removing the unexposed part of the second conductive filmwhich is not covered with the photoresist film, thereby leaving theother part of the second conductive film in the trench or the throughhole.

[0023] (2) In the method of manufacturing a semiconductor integratedcircuit device device. described in Paragraph M. the second conductivefilm may be removed in part in the step (e) by means of etching usingthe Photoresist film as a mask.

[0024] (3) In the method of manufacturing a semiconductor integratedcircuit device device, described in paragraph (1), the second conductivefilm May be removed in part in the step (e) by means of chemicalmechanical Polishing.

[0025] (4) In the method of manufacturing a semiconductor integratedcircuit device device, described in Paragraph (1), wherein thephotoresist film may be removed in part in the step (d) by developingthe photoresist film.

[0026] (5) The method of manufacturing a semiconductor integratedcircuit device, described in paragraph (1), after the step (e) has beenperformed, may further comprise a step (f) of removing that part of thephotoresist film lying in the trench or the through hole and growing athird conductive film on the second conductive film exposed in thetrench or the through hole, thereby burying the third conductive film inthe trench or the through hole.

[0027] (6) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (5), the second conductive filmmay be made of titanium nitride or tungsten.

[0028] (7) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (5), the third conductive filmmay be made of tungsten or aluminum alloy.

[0029] (8) The method of manufacturing a semiconductor integratedcircuit device, described in paragraph (5), after the step (f) has beenperformed, may further comprise a step (h) of forming a fourthconductive film on the first insulating film and electrically connectingthe fourth conductive film to the first conductive film via the thirdconductive film in the trench or the through hole.

[0030] (9) The method of manufacturing a semiconductor integratedcircuit device, described in paragraph (1), may further comprise thefollowing steps (f) and (g) which are performed after the step (e):

[0031] (f) removing that part of the photoresist film which lie in thetrench or the through hole, and forming a fifth conductive film in thetrench or the through hole and on the first insulating film; and

[0032] (g) growing a sixth conductive film on the fifth conductive filmand removing those parts of the sixth and fifth conductive films whichlie outside the trench or the through hole, thereby leaving the sixthand fifth conductive film in the trench or the through hole.

[0033] (10) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (9), the second conductive filmmay be made of titanium nitride or tantalum nitride.

[0034] (11) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (9), the fifth and sixthconductive films may be made of copper.

[0035] (12) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (9), said parts of the sixth andfifth conductive films may be removed by means of chemical mechanicalpolishing.

[0036] (13) A method of manufacturing a semiconductor integrated circuitdevice, according to the present invention, is one designed tomanufacture a semiconductor integrated circuit device that has at leastone memory cell composed of a cell-selecting MISFET formed in a majorsurface of a semiconductor substrate and a data-storing capacitiveelement provided above the cell-selecting MISFET. This method comprisesthe steps of:

[0037] (a) forming a cell-selecting MISFET on in a major surface of asemiconductor substrate, forming a first insulating film on thecell-selecting MISFET, and forming, in a through hole made in the firstinsulating film, a first conductive film electrically connected to asource or drain of the cell-selecting MISFET;

[0038] (b) forming a second insulating film on the first insulating filmand making a trench in the second insulating film;

[0039] (c) forming a second conductive film in the trench and on thesecond insulating film, said second conductive film extending throughthe trench and electrically connected to the first conductive film;

[0040] (d) covering the second conductive film with a photoresist filmand applying exposure light to the photoresist' film, thereby exposingthat part of the photoresist film which lies outside the trench tolight;

[0041] (e) removing that part of the photoresist film Which has beenexposed to light. thereby leaving, in the trench, that part of thephotoresist film which is not exposed to light;

[0042] (f) removing that part of the second conductive film which is notcovered with the photoresist film, thereby leaving the other part of thesecond conductive film in the trench; and

[0043] (g) removing that part of the photoresist film that lies in thetrench, and then forming a third insulating film in the trench and onthe second insulating film and forming is a third conductive film on thethird insulating film, thereby forming a data-storing capacitive elementcomposed of a first electrode, a capacitive insulating film and a secondelectrode which are made of the second conductive film, third insulatingfilm and third conductive film, respectively.

[0044] (14) A method of manufacturing a semiconductor integrated circuitdevice, according to the invention, is one designed to manufacture asemiconductor integrated circuit device that has at least one memorycell composed of a cell-selecting MISFET formed in a major surface of asemiconductor substrate and a data-storing capacitive element providedabove the cell-selecting MISFET. This method comprises the steps of:

[0045] (a) forming a cell-selecting MISFET on the major surface of thesemiconductor substrate, forming a first insulating film on thecell-selecting MISFET, and forming, in a through hole made in the firstinsulating film, a first conductive film electrically connected to asource or drain of the cell-selecting MISFET;

[0046] (b) forming a second insulating film on the first insulating filmand making a trench in the second insulating film;

[0047] (c) forming, in the trench and on the second insulating film, asecond conductive film made of amorphous silicon and electricallyconnected to the first conductive film via the trench;

[0048] (d) covering the second conductive film with a photoresist filmand applying exposure light to the photoresist film, thereby exposingthat part of the photoresist film which lies outside the trench tolight;

[0049] (e) removing that part of the photoresist film which has beenexposed to light, thereby leaving, in the trench, that part of thephotoresist film which is not exposed to light;

[0050] (f) removing that part of the second conductive film which is notcovered with the photoresist film, thereby leaving the second conductivefilm in the trench;

[0051] (g) removing that part of the photoresist film which lies in thetrench and forming depressions and projections in and on the surface ofthe second conductive film exposed in the trench;

[0052] (h) heat-treating the second conductive film, converting the sameto a polycrystalline film; and

[0053] (i) forming a third insulating film in the trench and on thesecond insulating film and forming a third conductive film on the thirdinsulating film, thereby forming a data-storing capacitive elementcomposed of a first electrode, a capacitive insulating film and a secondelectrode which are made of the second conductive film, third insulatingfilm and third conductive film, respectively.

[0054] (15) A method of manufacturing a semiconductor integrated circuitdevice, according to the invention, is one designed to manufacture asemiconductor integrated circuit device that has at least one memorycell composed of a cell-selecting MISEET formed in a major surface of asemiconductor substrate and a data-storing capacitive element providedabove the cell-selecting MISFET. The method comprises the steps of:

[0055] (a) forming a cell-selecting MISFET on a major surface of asemiconductor substrate, forming a first insulating film on thecell-selecting MISFET, and forming, in a through hole made in the firstinsulating film, a first conductive film electrically connected to asource or drain of the cell-selecting MISFET;

[0056] (b) forming a second insulating film on the first insulating filmand then making a trench in the second insulating film;

[0057] (c) forming, in the trench and on the second insulating film, asecond conductive film made of amorphous silicon and electricallyconnected to the first conductive film via the trench;

[0058] (d) forming depressions and projections in and on the surface ofthe second conductive film;

[0059] (e) heat-treating the second conductive film, converting the sameto a polycrystalline film; and

[0060] (f) covering the second conductive film with a photoresist filmand applying exposure light to the photoresist film, thereby exposingthat part of the photoresist film which lies outside the trench tolight;

[0061] (g) removing that part of the photoresist film which has beenexposed to light, thereby leaving that part of the photoresist filmwhich lies in the trench;

[0062] (h) removing that part of the second conductive film which is notcovered with the photoresist film, thereby leaving the second conductivefilm in the trench;

[0063] (i) removing that part of the photoresist film which lies in thetrench, then forming a third insulating-film in the trench and on thesecond insulating film and forming a third conductive film on the thirdinsulating film, thereby forming a data-storing capacitive elementcomposed of a first electrode, a capacitive insulating film and a secondelectrode which are made of the second conductive film, third insulatingfilm and third conductive film, respectively.

[0064] (16) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (14), that part of the secondconductive film which is not covered with the photoresist film may beremoved by means of etching using the photoresist film as a mask.

[0065] (17) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (14), the depressions andprojections may be formed in and on the second conductive film, bygrowing silicon grains on the surface of the second conductive film madeof amorphous silicon.

[0066] (18) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (14), wherein when that part ofthe second conductive film which is not covered with the photoresistfilm is removed, an upper edge of that part of the second conductivefilm which lies in the trench is made to recede below a rim of thetrench.

[0067] (19) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (18), the upper edge of thesecond conductive film may be made to recede by a distance substantiallyequal to a diameter of the depressions and projections formed in and onthe surface of the second conductive film.

[0068] (20) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (13), the second insulating filmmay be a silicon oxide film.

[0069] (21) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (13), the third insulating filmmay be a film having a large dielectric constant or a ferroelectricfilm.

[0070] (22) A method of manufacturing a semiconductor integrated circuitdevice, according to the present invention, comprises the steps of:

[0071] (a) forming a first conductive film on a major surface of asemiconductor substrate, forming a first insulating film on the firstconductive film and then making a through hole in the first insulatingfilm;

[0072] (b) forming a photoresist film in the through hole and on thefirst insulating film, and then exposing to light a part of thephotoresist film which lies in the through hole and a part of the partof the photoresist film which lies on a wire-forming region;

[0073] (c) removing the part of the photoresist film which has beenexposed to light, thereby leaving the unexposed parts of the photoresistfilm which lie on a part of the first insulating film and in the throughhole;

[0074] (d) etching the first insulating film by using the unexposed partof the photoresist film as a mask, thereby making a wire trench in thefirst insulating film;

[0075] (e) removing the unexposed part of the photoresist film andforming a second conductive film, on the first insulating film and inthe wire trench and through hole, said second conductive film lying inthe through hole and electrically connected to the first conductive filmvia the through hole; and

[0076] (f) removing the part of the second conductive film which lies onthe first insulating film by means of chemical and mechanical polishing,thereby forming a buried wire made of the second conductive film in thewire trench and through hole.

[0077] (23) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (22), the second conductive filmmay be made of copper.

[0078] (24) A method of manufacturing a semiconductor integrated circuitdevice, according to the present invention, comprises the steps of:

[0079] (a) forming a first conductive film on a major surface of asemiconductor substrate, forming a first insulating film on the firstconductive film and then patterning the first insulating film and firstconductive film, thereby forming a gate electrode made of the firstconductive film and covered with the first insulating film;

[0080] (b) forming semiconductor regions in two parts of thesemiconductor substrate lie at both sides of the gate electrode;

[0081] (c) forming a second insulating film on the semiconductorsubstrate, covering the gate electrode formed on the semiconductorsubstrate and then forming a third insulating film on the secondinsulating film, said third insulating film having an etching ratedifferent from that of the second insulating film;

[0082] (d) etching the third insulating film by using a firstphotoresist film as a mask, thereby making -a first trench reaching thesecond insulating film provided on the semiconductor region and making asecond trench reaching the second insulating film provided on the gateelectrode;

[0083] (e) removing the first photoresist film and forming a secondphotoresist film in the first and second trenches and on the thirdinsulating film;

[0084] (f) applying exposure light to the second photoresist film,thereby exposing to light those parts of the second photoresist filmwhich lie in the second trench and on the third insulating film, andremoving those parts of the second resist film which have been exposedto light, thereby leaving an unexposed part of the second photoresistfilm in the first trench;

[0085] (g) etching a part of the second insulating film and a part ofthe first insulating film lying beneath the second insulating film, byusing the second photoresist film left in the first trench as a mask;and

[0086] (h) removing the second photoresist film and etching the secondinsulating film lying in the first trench and the first insulating filmlying in the second trench, thereby making a first contact hole exposingthe semiconductor region and a second contact hole exposing the gateelectrode.

[0087] (25) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (24), the first and secondinsulating films may be made of silicon nitride and the third insulatingfilm is made of silicon oxide film.

[0088] (26) The method of manufacturing a semiconductor integratedcircuit device, described in paragraph (24) may comprises the followingsteps (i) and (J) which are performed after the step (h):

[0089] (i) forming a second conductive film in the first and secondcontact holes and on the third insulating film; and

[0090] (j) patterning the second conductive film, thereby forming firstand second wires in the first and second contact holes, which areelectrically connected to the semiconductor region and the gateelectrode, respectively.

[0091] (27) A method of manufacturing a semiconductor integrated circuitdevice, according to this invention, comprises the following steps:

[0092] (a) forming a trench in a first insulating film provided on amajor surface of a semiconductor substrate and forming a silicon layerin the trench and on the first insulating film;

[0093] (b) forming a second insulating film on the silicon layer layingin the trench and removing that part of the silicon layer which liesoutside the trench;

[0094] (c) removing that part of the second insulating film which liesin the trench and forming depressions and projections in and on thesilicon layer; and

[0095] (d) forming a dielectric film on the silicon having thedepressions and projections in and on the surface, and forming aconductive film on the dielectric film.

[0096] (28) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (27), the silicon layer may bemade of amorphous silicon.

[0097] (29) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (27), the first insulating filmmay be made of silicon oxide and the second insulating film is made ofphotoresist.

[0098] (30) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (27), the depressions andprojections provided in and on the silicon layer may be ones formed bygrowing silicon grains on the surface of the silicon layer.

[0099] (31) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (29), the step (b) may includethe following sub-steps:

[0100] (b-1) forming a photoresist film in the trench and on the firstinsulating film and then applying exposure light to the photoresistfilm, thereby applying light to that part of the photoresist film whichlies outside the trench;

[0101] (b-2) removing that part of the photoresist film which has beenexposed to light, thereby leaving an unexposed part of the photoresistfilm in the trench; and

[0102] (b-3) removing that part of the silicon layer which lies outsidethe trench, by means of etching using the photoresist film as a mask.

[0103] (32) In the method of manufacturing a semiconductor integratedcircuit device, described in paragraph (27), the Silicon layer havingthe depressions and projections in and on the surface may constitute afirst electrode of a capacitive element, the dielectric film mayconstitute a capacitive insulating film of the capacitive element, andthe Conductive film may constitute a second electrode of the capacitiveelement.

[0104] (33) A method of manufacturing a semiconductor integrate circuit,according to the present invention, comprises the following steps:

[0105] (a) making a trench in a first insulating film provided on amajor surface of a semiconductor substrate and then forming a conductivelayer in the trench and on the first insulating film;

[0106] (b) forming a photoresist film on the conductive layer andapplying exposure light to the photoresist film, thereby exposing tolight the entire surface of the photoresist film and a part of thephotoresist film which lies in the trench;

[0107] (c) developing the photoresist film, thereby removing that partof the photoresist film which has been entirely exposed to light andleaving that unexposed part of the photoresist film which lies in thetrench; and

[0108] (d) removing the unexposed part of the conductive layer which isnot covered with the photoresist film.

[0109] (34) In the method of manufacturing a semiconductor integratecircuit, described in paragraph (33), that part of the conductive layermay be removed by means of etching using the photoresist film as a mask.

[0110] (35) A method of manufacturing a semiconductor integrate circuit,according to the invention, comprises the following steps:

[0111] (a) forming a silicon oxide film on a major surface of asemiconductor substrate and making a trench in the silicon oxide film;

[0112] (b) forming a first conductive film in the trench and on thesilicon oxide film;

[0113] (c) covering the first conductive film with a photoresist filmand applying exposure light to the photoresist film, thereby exposing tolight that part of the photoresist film which lies outside the trench;

[0114] (d) developing that part of the photoresist film which has beenexposed to light, thereby leaving the unexposed part of the photoresistfilm in the trench;

[0115] (e) removing the unexposed-part of the first conductive filmwhich lies on the silicon oxide film, by means of etching using thephotoresist film as a mask; and

[0116] (f) removing that part of the photoresist film which lies in thetrench, thereby leaving that part of the first conductive film whichlies in the trench.

[0117] (36) In the method of manufacturing a semiconductor integratecircuit, described in paragraph (35), the photoresist film may beremoved in the step (f by means of ashing.

BRIEF DESCRIPTIONS OF THE DRAWINGS

[0118]FIG. 1 is a sectional view of a semiconductor substrate,illustrating a method of manufacturing a semiconductor integratedcircuit device, i.e. Embodiment 1 of the present invention;

[0119]FIG. 2 is a sectional view of the semiconductor substrate,explaining the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 1 of this present invention;

[0120]FIG. 3 is a sectional view of the semiconductor substrate,explaining the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 1 of the invention;

[0121]FIG. 4 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 1 of the invention;

[0122]FIG. 5 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 1 of this invention;

[0123]FIG. 6 is a sectional view of the semiconductor substrate,explaining the method of manufacturing a semiconductor Integratedcircuit device, i.e., Embodiment 1 of the present invention;

[0124]FIG. 7 is a sectional view of the semiconductor substrate, showingthe method of manufacturing a semiconductor integrated circuit device,i.e., Embodiment 1 of the present invention;

[0125]FIG. 8 is a sectional view of the semiconductor substrate,explaining the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 1 of this invention;

[0126]FIG. 9 is a sectional view of the semiconductor substrate,Illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 1 of the invention;

[0127]FIG. 10 is a sectional view of the semiconductor substrate,explaining the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 1 of the invention;

[0128]FIG. 11 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor Integrated circuitdevice, i.e., Embodiment 1 of the present invention;

[0129]FIG. 12 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 1 of the invention;

[0130]FIG. 13 is a sectional view of the semiconductor substrate,explaining the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 1 of this invention;

[0131]FIG. 14 is a sectional view of the semiconductor substrate,explaining the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 1 of the invention;

[0132]FIG. 15 is a sectional view of a semiconductor substrate, showinga method of manufacturing a semiconductor integrated circuit device,i.e., Embodiment 2 of this invention;

[0133]FIG. 16 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 2 of the present invention;

[0134]FIG. 17 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 2 of the invention;

[0135]FIG. 18 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 2 of the invention;

[0136]FIG. 19 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 2 of this invention;

[0137]FIG. 20 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 2 of the present invention;

[0138]FIG. 21 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 2 of the invention;

[0139]FIG. 22 is a sectional view of a semi-conductor substrate, showingthe method of manufacturing a semiconductor integrated circuit device,i.e., Embodiment 3 of the present invention;

[0140]FIG. 23 is a sectional view of the semiconductor substrate,Illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 3 of the present Invention;

[0141]FIG. 24 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 3 of this invention;

[0142]FIG. 25 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor Integrated circuitdevice, i.e., Embodiment 3 of the invention;

[0143]FIG. 26 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 3 of this invention;

[0144]FIG. 27 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 3 of the invention;

[0145]FIG. 28 Is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 3 of the invention;

[0146]FIG. 29 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 3 of the present invention;

[0147]FIG. 30 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor Integrated circuitdevice, i.e., Embodiment 3 of the invention;

[0148]FIG. 31 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 3 of this invention;

[0149]FIG. 32 Is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 3 of the invention;

[0150]FIG. 33 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 3 of the invention;

[0151]FIG. 34 is a sectional view of a semiconductor substrate,depicting a method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 4 of the present invention;

[0152]FIG. 35 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 4 of the invention;

[0153]FIG. 36 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 4 of this invention;

[0154]FIG. 37 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 4 of the invention;

[0155]FIG. 38 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 4 of the present invention;

[0156]FIG. 39 is a sectional view of the semiconductor substrate,Illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 4 of the invention;

[0157]FIG. 40 Is a sectional view of a semiconductor substrate,illustrating a method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 5 of the present invention;

[0158]FIG. 41 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 5 of the invention;

[0159]FIG. 42 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 5 of the invention;

[0160]FIG. 43 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 5 of this invention;

[0161]FIG. 44 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, I.e., Embodiment 5 of the present invention;

[0162]FIG. 45 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor Integratedcircuit device, i.e., Embodiment 5 of the invention;

[0163]FIG. 46 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 5 of this invention;

[0164]FIG. 47 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 5 of this invention;

[0165]FIG. 48 Is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 5 of the invention;

[0166]FIG. 49 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 5 of the invention;

[0167]FIG. 50 is a sectional view of a semiconductor substrate,illustrating a method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 6 of the present Invention;

[0168]FIG. 51 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 6 of the invention;

[0169]FIG. 52 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 6 of the invention;

[0170]FIG. 53 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 6 of this invention;

[0171]FIG. 54 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 6 of the present invention;

[0172]FIG. 55 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 6 of the invention;

[0173]FIG. 56 is a sectional view of the semiconductor substrate,depicting the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 6 of this invention;

[0174]FIG. 57 is a sectional view of the semiconductor substrate,illustrating the method of manufacturing a semiconductor integratedcircuit device, i.e., Embodiment 6 of the invention; and

[0175]FIG. 58 is a sectional view of the semiconductor substrate,showing the method of manufacturing a semiconductor integrated circuitdevice, i.e., Embodiment 6 of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0176] Embodiments of the present invention will be described in detail,with reference to the accompanying drawings. In the drawingsillustrating the embodiments, the components of any embodiment, whichperform the same functions as those of any other embodiment, aredesignated with the same reference numerals and symbols and will not bedescribed repeatedly.

[0177] (Embodiment 1)

[0178] The method of manufacturing a DRAM (Dynamic Random AccessMemory), which is Embodiment 1 of the present invention, will beexplained, by describing the sequence of manufacturing steps, withreference to FIGS. 1 to 14.

[0179] First, as shown in FIG. 1, element-isolating trenches 2 are madein the surface of a semiconductor substrate 1 (hereinafter referred toas “substrate”) that is made of, for example, p-type single crystalsilicon. More specifically, those parts of the substrate 1 are etchedaway thereby making the trenches 3. Silicon oxide is deposited in thetrenches 3 and on the substrate 1 by means of CVD (Chemical VaporDeposition). The silicon oxide on the substrate 1 is removed by CMP(Chemical Mechanical Polishing), thereby forming silicon oxide film 5 inthe trenches 3. Thereafter, p-type impurities (boron (B)) areion-implanted into the substrate 1 thereby forming a p-type well 3 inthe major surface of the substrate 1.

[0180] Next, the substrate 1 is subjected to steam oxidation thusforming a gate insulating film 6 on the surface of the p-type well 3.Gate electrodes 7 (word lines WL) are formed on the gate insulating film6, in the following manner. First, a polycrystalline silicon film dopedwith n-type impurities, such as phosphorus (P), is deposited on thesubstrate 1 by CVD. Then, a tungsten nitride (WN) film is formed on thepolycrystalline silicon film by sputtering. Further, a tungsten (W) filmis deposited on the tungsten nitride film by sputtering. Then, a siliconnitride film 8 is formed on the tungsten film by CVD. And then, thetungsten nitride film, the tungsten film and the silicon nitride film 8are patterned by dry etching using a photoresist film as a mask.

[0181] As shown in FIG. 2, n-type impurities, such as phosphorus (P),are ion-implanted into those parts of the p-type wells 3, which areamong the gate electrodes 7. N⁻-type semiconductor regions 9 are therebyformed. A silicon nitride film 10 is deposited on the gate electrodes 7(word lines WL) by CVD, and a silicon oxide film. 11 is also depositedon the silicon nitride film 10 by CVD. Chemical mechanical polishing isperformed on the silicon oxide film 11 such that the film 11 has a flatupper surface.

[0182] Then, as shown in FIG. 3, the silicon oxide film 11 and siliconnitride film 10 are subjected to dry etching using a photoresist film(not shown) as a mask. Contact holes 12 and 13 are thereby made abovethe n⁻-type semiconductor regions 9, respectively. The silicon oxidefilm 11 is etched at a rate much higher than the rate at which thesilicon nitride film 10 is etched, thus preventing the silicon nitridefilm 10 lying beneath the silicon nitride film 11 from being removed.The silicon nitride film 10 is etched at a rate much higher than therate at which the substrate I is etched, thereby preventing thesubstrate 1 from being etched excessively deep. Moreover, the siliconnitride film 10 is subjected to anisotropic etching, thereby leaving thesilicon nitride film 10 on the sides of each gate electrode 7 (word lineWL). As a result, the contact holes 12 and 13 are self-aligned withrespect to the gate electrodes 7 (word lines WL). Hence, there is noneed to provide a margin for the alignment between the contact holes 12,13 and the gate electrodes 7 (word lines WL). This helps to decrease thesize of the memory cells of the DRAM.

[0183] Next, n-type impurities such as arsenic (As), are ion-implantedinto the p-type well 3 through the contact holes 12 and 13 therebyforming n⁺-type semiconductor regions 14 (sources and drains). Themanufacturing steps, described thus far, form n-channel MISFETs Qs, eachhaving a gate insulating film 6, a gate electrode 7 and n⁺-typesemiconductor regions 14 (source and drain) and used to select a memorycell.

[0184] Further, plugs 15 are formed in the contact holes 12 and 13. Morespecifically, the plugs 15 are formed in the following way. First,low-resistance polycrystalline silicon films doped with n-typeimpurities, such as phosphorus, are deposited in the contact holes 12and 13 and on the silicon oxide film 11 by means of CVD. Then, thepolycrystalline silicon film that lies on the silicon oxide film 11 isremoved by dry etching (or by chemical mechanical polishing). Thepolycrystalline silicon film is thereby left in the contact holes 12 and13 only.

[0185] As shown in FIG. 4, a silicon oxide film 16 is deposited on thesilicon oxide film 11 by means of CVD. Dry etching using a photoresistfilm (not shown) as a mask is performed on the silicon oxide film 16 tomake a through hole 17 that communicates with the contact hole 12. Aplug 18 is then formed in the through hole 17. Further, a bit line BL isformed on the plug 18.

[0186] More precisely, the plug 18 is formed by the following method.First, a titanium nitride film is deposited in the through hole 17 andon the silicon oxide film 16 by means of sputtering. Then, a tungstenfilm is deposited in the through hole 17 and on the titanium nitridefilm also by of sputtering. Thereafter, the titanium nitride film andthe tungsten film, except the parts in the through hole 17, are removedby chemical mechanical polishing. The bit line BL is formed in thefollowing manner. First, a tungsten film is deposited on the siliconoxide film 16 by means of sputtering. Then, dry etching using aphotoresist film (not shown) as a mask is carried out, thus patterningthe tungsten film. The bit line BL thus formed is electrically connectedby the plugs 18 and 15 formed in the through holes 17 and 12,respectively, to the drain or source (i.e., n⁺-type semiconductor region14) of the cell-selecting MISFET Qs.

[0187] Next, a silicon oxide film 19 is deposited on the silicon oxidefilm 16 by means of CVD. The silicon oxide films 19 and 16 are subjectedto dry etching using a photoresist film (not shown) as a mask, thusmaking through holes 21. A plug 22 is formed in each of the throughholes 21 in the following way. First, a low-resistance polycrystallinesilicon film doped with n-type impurities such as phosphorus (P) isdeposited by CVD in the through hole 21 and on the silicon oxide film19. Then, that part of the polycrystalline silicon film which isprovided on the silicon oxide film 19 is removed by dry etching (or bychemical mechanical polishing), thereby leaving the polycrystallinesilicon film in the through hole 21 only.

[0188] As shown in FIG. 5, a silicon nitride film 23 is deposited on thesilicon oxide film 19 by CVD. Then, a silicon oxide film 24 is depositedon the silicon nitride film 23 by CVD, too. The silicon oxide film 24and silicon nitride film 23 are subjected to dry etching using aphotoresist film (not shown) as a mask, thereby making trenches 25 whichare aligned with the through holes 21. The lower electrodes ofdata-storing capacitive elements (later described) will be formed on theinner walls of these trenches 25. The silicon oxide film 24 musttherefore have a large thickness (1 μm or more) to impart a large areato the lower electrodes, thereby to increase the charge that eachcapacitive element may accumulates.

[0189] The silicon oxide film 24 is etched at a rate higher than therate at which the silicon nitride film 23 may be etched. This preventsthe silicon nitride film 23, which lies beneath the silicon oxide film24, from being removed. The silicon nitride film 23 is etched at a ratehigher than the rate at which the silicon oxide film 19 may be etched.This prevents the silicon oxide film 19 from being etched too deep. Thesilicon nitride film 23 provided beneath the thick silicon oxide film 24functions as an etching stopper, preventing the silicon oxide film 19from being etched excessively when the silicon oxide film 24 is etchedto make the trenches 25. The trenches 25 can therefore be made with highprecision.

[0190] Thereafter, as shown in FIG. 6, an amorphous silicon film 26Adoped with n-type impurities Such as phosphorus is deposited in thetrenches 25 and the silicon oxide film 24 by means of CVD. The amorphoussilicon film 26A is deposited to a small thickness (e.g., 50 to 60 nm)thereby only covering the inner surfaces of the trenches 25.

[0191] As shown In FIG. 7, a photoresist film 30 is formed on theamorphous silicon film 26A by spin-coating. The photoresist film 30 ismade of positive-type photoresist (e.g., photoresist mainly made ofnovolac resin).

[0192] Then, as FIG. 8 shows, exposure light is applied to the entiresurface of the photoresist film 30. At this time, those parts of thephotoresist film 30, which exist outside the trenches 25 and near therims thereof. are exposed to light. By contrast, the other partsprovided near the bottoms of the trenches 25 are not thoroughly exposedto light, because the exposure light reaching the bottoms of thetrenches 25 are weak.

[0193] As shown in FIG. 9, the photoresist film 30 is developed withalkali aqueous solution or the like. Those parts of the photoresist film30, which exist outside the trenches 25 and near the rims thereof, areremoved because they are soluble with the developing solution. On theother hand, the other parts of the film 30, which are provided near thebottoms of the trenches 25, are not removed because they have notsufficiently exposed. As a result, those parts of the amorphous siliconfilm 26A, that are outside the trenches 25, are exposed. The other partsof the film 26A, which exist in the trenches 25, remain covered with thephotoresist film 30, except for those parts that are provided near therims of the trenches 25.

[0194] Next, as shown in FIG. 10, those parts of the amorphous siliconfilm 26A, which are not covered with the photoresist film 30, i.e., theparts outside the trenches 25 and near the rims thereof, are removed bymeans of dry etching. The amorphous silicon film 26A is etched at a ratemuch higher than the rate at which the photoresist film 30 may beetched. This prevents those parts of the amorphous silicon film 26A,which are covered with the photoresist films 30 Provided in the trenches25, from being exposed and etched away.

[0195] It is desired that the amorphous silicon film 26A is subjected toanisotropic etching such that the upper edges of the amorphous siliconfilms 26 in the trenches 25 may recede downwards a little from the rimsof the trenches 25. If the upper edges of the amorphous silicon films 26so recede downwardly, an electric field will scarcely concentrate at thedistal ends (upper edges) of the lower electrodes formed in the trenches25. It is therefore possible to decrease the leakage current of thedata-storing capacitive elements. It is desirable to make the upperedges of the amorphous silicon films 26 recede from the rims of thetrenches 25 by a distance (about 50 nm) that is almost equal to thediameter of silicon grains grown in the surface of the amorphous siliconfilm 26A. If the upper edges of the amorphous silicon films 26 recedeshorter than this distance, the silicon grains will protrude from therims of the trenches 25, and an electric field will concentrate at thesilicon grains. Conversely, if the upper edges of the amorphous siliconfilms 26 recede longer than this distance, the surface of the lowerelectrode of each capacitive element will decrease, inevitably reducingthe charge the capacitive element can accumulate.

[0196] Then, as shown in FIG. 11, those parts of the photoresist film 30which remain in each trench 25 are removed by means of, for example,ozone ashing. Specifically, the photoresist film 30 is oxidized anddecomposed with the oxygen radicals generated by thermally decomposingozone. This ashing is conducted in such a manner that the oxygenradicals are generated in great numbers and for a long time. Many oxygenradicals, so generated, decompose and remove the photoresist film 30completely from the amorphous silicon film 26A provide in each trench 25(that is relatively deep).

[0197] During the dry etching of those parts of the amorphous siliconfilms 26A, which are outside the trenches 25, the photoresist film 30protects the other parts of the amorphous silicon films 26A, which areprovided in the trenches 25. Thereafter, the photoresist film 30, whichis no longer necessary, is removed by means of ashing. With this methodit is possible to minimize the etching of the other parts of the films26A which exist in the trenches 25, in the course of removing thoseparts of the amorphous silicon films 26A which are outside the trenches25. This is because the amorphous silicon film 26A is etched at a ratehigher than the rate at which the photoresist film 30 may be etched.Since the photoresist film 30 is removed from the trenches 25 by meansof ashing, it is also possible to minimize the etching of those parts ofthe silicon oxide film 24 provided outside the trenches 25.

[0198] Next, as shown in FIG. 12, the amorphous silicon films 26A thatexist in the trenches 25, are processed by forming polycrystallinesilicon films 26 with a rough surface. More precisely, the surfaces ofthe amorphous silicon films 26A are washed with, for example, ahydrofluoric acid-based washing solution. Then, monosilane (SiH₄) ordisilane (Si₂H₆) is applied to the amorphous silicon film 26A in apressure-reduced atmosphere. Silicon grains with an average diameter ofabout 50 nm are thereby grown on the surface of each amorphous siliconfilm 26A. Thereafter, the substrate 1 is heat-treated thereby convertingthe amorphous silicon films 26 to polycrystalline silicon films 26.Having a rough surface, each polycrystalline silicon film 26 has a largesurface area. This renders it possible to increase the charges thedata-storing capacitive element can accumulate.

[0199] In the present embodiment, the amorphous silicon films 26Aprovided in the trenches 25 have their surfaces roughened after thephotoresist film 30 (protecting the films 26A) is removed by means ofashing. Therefore, those parts of the photoresist film 30, which remainin the trenches 25, can be easily removed. If a protection film isformed on the amorphous silicon films 26A after roughening the surfacesof the amorphous silicon films 26A and removed after etching away theamorphous silicon films 26A, the protection film would likely remain inthe depressions made in the surface of each film 26A and between theprojections formed on the surface thereof.

[0200] As shown in FIG. 13, a tantalum oxide (Ta₂O₅) film 28 is formedon the exposed top of the silicon oxide film 24 and on thepolycrystalline silicon films 26 provided in the trenches 25. Thetantalum oxide film 26, which has a large dielectric constant, is formedby thermal CVD in which pentaethoxy tantalum and oxygen are used assource gases. The film 26 has a thickness of about 20 m. Before thetantalum oxide film 26 is formed, the polycrystalline silicon film 26 isnitrided thereby forming a thin silicon nitride film on eachpolycrystalline silicon film 26. In this case, the thin silicon filmreduces the leakage current in the tantalum oxide film 28. Thereafter,the tantalum oxide film 28 is changed and crystallized in an oxygenatmosphere at about 800° C. As a result, a tantalum oxide film 28 isobtained, which has a large dielectric constant and in which the leakagecurrent is small.

[0201] As shown in FIG. 14, CVD and sputtering are carried out,depositing a titanium nitride (TiN) film 29 on the tantalum oxide film28. As a result, data-storing capacitive elements C are formed. Eachcapacitive element C comprises a lower electrode made of thepolycrystalline silicon film 26, a capacitance insulating film made ofthe oxide tantalum film 28, and an upper electrode made of the siliconnitride film 29. The lower electrode (i.e., the polycrystalline siliconfilm 26) of each data-storing capacitive element C is electricallyconnected to the other of the source and drain (i.e., n⁺-typesemiconductor regions 14) of the cell-selecting MISFET Qs by the plugs22 and 15 that are formed in the through hole 21 and the contact hole13, respectively. Thus, the memory cells of the DRAM are made, eachcomprising a cell-selecting MISFET Qs and a data-storing capacitiveelement C connected in series to the MISFET Qs.

[0202] Thereafter, aluminum (Al) wires, each comprising two layers, areformed on the data-storing capacitive elements C. A passivation film isformed to cover the aluminum wires. The passivation film is a two-layerfilm composed of a silicon oxide film and a silicon nitride film formedon the silicon oxide film. Neither the aluminum wires nor thepassivation film is illustrated in FIG. 14 and will not be described indetail.

[0203] In the present embodiment, the lower electrodes formed in thetrenches 25 made in the surface of the silicon oxide film 24 a made ofthe polycrystalline silicon film 26. Nonetheless, the material of thelower electrodes is not limited to polycrystalline silicon. Nor thematerials of the capacitance insulating film and upper electrode arelimited to tantalum oxide and titanium nitride, respectively. Rather,the lower electrodes and upper electrodes may be made of tungsten,platinum, ruthenium, iridium or the like. The capacitance insulatingfilm may be made of a metal oxide having a large dielectric constant ora ferroelectric material. To be more specific, the capacitance insultingfilm may be made of BST, STO, BaTi0₃ (barium titanate), PbTi0₃ (leadtitanate), PZT (PbZrX Ti1—X0₃), PLT (PbLaX Ti1—X0₃), or PUT.

[0204] (Embodiment 2)

[0205] The method of manufacturing a DRAM (Dynamic Random AccessMemory), which is Embodiment 2 of the invention, will be described withreference to FIGS. 15 to 21. Embodiment 2 is differs from Embodiment 1in the way of forming the lower electrodes (i.e., the polycrystallinesilicon films 26) of the data-storing capacitive elements C.

[0206] First, as shown in FIG. 15, a silicon nitride film 23 and a thicksilicon oxide film 24 are deposited above the silicon oxide film 19 thatcovers a bit line BL. Deep trenches 25 are made in the silicon oxidefilm 24 and the silicon nitride film 23. And then, an amorphous siliconfilm 26A is deposited in the trenches 25 and on the silicon oxide film24. These steps of manufacturing the DRAM are identical to the steps ofEmbodiment 1, shown in FIGS. 1 to 6.

[0207] Next, as shown in FIG. 16, silicon grains are grown in thesurface of the amorphous silicon film 26A. The substrate 1 is thenheat-treated thus converting the amorphous silicon film 26A to apolycrystalline silicon film 26. The polycrystalline silicon film 26 hasa rough surface, in the trenches 25 and at the upper surface of thesilicon oxide film 24. The surface of the amorphous silicon film 26A isroughened in the same manner as in Embodiment 1.

[0208] As shown in FIG. 17, a positive-type photoresist film 30 isformed on the polycrystalline silicon film 26 by means of spin-coating.Exposure light is applied to the entire photoresist film 30. As shown inFIG. 18, the photoresist film 30 is developed. Those parts of the film30 that have been exposed to light are removed. The other parts of thefilm 30, which have not been exposed to light, remain in the trenches25.

[0209] Then, as shown in FIG. 19, those parts of the polycrystallinesilicon film 26, which are not covered with the photoresist film 30 andpresent near the upper edges of the trenches 25, are removed by means ofdry etching. The polycrystalline silicon film 26 is etched at a ratemuch higher than the rate at which the photoresist film 30 may beetched, as the amorphous silicon film 26A is etched in Embodiment 1.This prevents the amorphous silicon film 26A, which is covered with thephotoresist film 30, from being exposed and etched. It is desired thatthe amorphous silicon film 26 is subjected to anisotropic etching, suchthat the upper edges of the amorphous Silicon films 26 near the Upperedges of the trenches 25 recede downwards a little from-the rims of thetrenches 25.

[0210] The etching of the polycrystalline silicon film 26, whose surfacehas been roughened, proceeds along the surface of the film 26. Hence,the parts of the film 26, which are on the rims of the trenches 25, mayremain not etched. These parts of the film 26, if not etched, will causeshort-circuiting between the lower electrodes formed in the trenches 25.The polycrystalline silicon film 26 must, therefore, be etched in suchconditions that no parts of the film 26 remain on the upper rims of thetrenches 25.

[0211] Next, as shown in FIG. 20, the photoresist film 30 is removedfrom the trenches 25 by means of, for example, the above-mentioned ozoneashing. The polycrystalline silicon films 26 provided in the trenches 25are thereby exposed. If photoresist remains among the silicon grains inthe surface of each polycrystalline silicon film 26, it will decreasethe charges the data-storing capacitive element C can accumulate.Therefore, the photoresist film 30 must be completely and thoroughly inspecific ashing conditions.

[0212] As shown in FIG. 21, a tantalum oxide film 28 is deposited on thesilicon oxide film 24 and on the polycrystalline silicon films 26provided in the trenches 25. Heat treatment is then effected, therebychanging and crystallizing the tantalum oxide film 28. A titaniumnitride film 29 is deposited on the tantalum oxide film 28. As a result,data-storing capacitive elements C are formed. Each capacitive element Ccomprises a lower electrode made of the polycrystalline silicon film 26,a capacitance insulating film made of the oxide tantalum film 28, and anupper electrode made of the titanium nitride film 29. The tantalum Oxidefilm 28 and the titanium nitride film 29 are formed in the Same way asin Embodiment 1.

[0213] In Embodiment 2, the photoresist film 30 protects those parts ofthe amorphous silicon films 26, which are provided in the trenches 25,during the dry etching of the other parts of the amorphous silicon films26 that are outside the trenches 25. Thereafter, the photoresist film30, which is no longer necessary, is removed by means of ashing. Withthis method it is possible to minimize the etching of the other parts ofthe films 26 which exist in the trenches 25, in the course of removingthose parts of the amorphous silicon films 26 which are outside thetrenches 25. This is because the amorphous silicon film 26 is etched ata rate higher than the rate at which the photoresist film 30 may beetched. Since the photoresist film 30 is removed from the trenches 25 bymeans of ashing, it is also possible to minimize the etching of thoseparts of the silicon oxide film 24 provided outside the trenches 25.

[0214] (Embodiment 3)

[0215] A method of forming plugs, which is Embodiment 3 of thisinvention, will be explained, by describing the sequence ofmanufacturing steps, with reference to FIGS. 22 to 33.

[0216] First, as shown in FIG. 22, element-isolating trenches 2 are madein the major surface of a semiconductor substrate 1 that is made of, forexample, p-type single crystal silicon. Thereafter, p-type impurities(boron (B)) are ion-implanted into one part of the substrate 1, therebyforming a p-type well 3 in the major surface of the substrate 1.Further, n-type impurities (phosphorus or arsenic) are ion-implantedinto another part of the substrate 1, thereby forming an n-type well 4.

[0217] Next, the CMOS process known in the art is performed, therebyforming an n-channel MISFET Qn in the p-type well 3 and a p-channelMISFET Qp in the n-type well 4. The n-channel MISFET Qn comprises a gateoxide film 6, a gate electrode 7 and n⁺-type semiconductor regions 31(source and drain). The p-channel MISFET Qp comprises a gate oxide film6, a gate electrode 7 and p⁺-type semiconductor regions 32 (source anddrain).

[0218] As shown in FIG. 23, a silicon oxide film 33 is deposited by CVDon the n-channel MISFET Qn and the p-channel MISFET Qp. And then, thesilicon oxide film 33 is subjected to chemical mechanical polishing toobtain a flat upper surface. The silicon oxide film 33 is then subjectedto dry etching using a photoresist film (not shown) as a mask. As aresult, contact holes 34 and 35 are made, respectively, which expose then⁺-type semiconductor regions 31, and contact holes 36 and 37 are made,respectively, which expose the p⁺-type semiconductor regions 32. At thesame time, a contact hole 38 is made, which exposes the gate electrode7.

[0219] Then, first-layer wires 41 to 47 are formed above the siliconoxide film 33. More specifically, the wires 41 to 47 are formed in thefollowing way. First, a titanium nitride film is deposited in thecontact holes 34 to 38 and on the silicon oxide film 33 by means ofeither sputtering or CVD. A tungsten film is deposited on the titaniumnitride film by means of CVD. Thereafter, dry etching using aphotoresist film as a mask is carried out, thereby patterning both thetungsten film and the titanium nitride film.

[0220] Plugs may be formed in the contact holes 34 to 38. In this case,a titanium nitride film is deposited in the contact holes 34 to 38 andon the silicon oxide film 33 by either sputtering or CVD. A tungstenfilm is then deposited on the titanium nitride film by means of CVD.Those parts of the tungsten film and the titanium nitride film, whichare provided on the silicon oxide film 33, are removed by chemicalmechanical polishing. Plugs are thereby formed in the contact holes 34to 38. Next, a tungsten film is formed on the silicon oxide film 33 bysputtering. Dry etching using a photoresist film as a mask is performed,thereby patterning the tungsten film. As a result, first-layer wires 41to 47 are formed.

[0221] Next, as shown in FIG. 24, a silicon oxide film 48 is depositedon the silicon oxide film 33 by means of CVD. The silicon oxide film 48is subjected to chemical mechanical polishing thus attaining a flatupper surface. Dry etching using a photoresist film (not shown) as amask is conducted on the silicon oxide film 48. Through holes 51 to 55are thereby made above the first-layer wires 41, 43, 44, 46 and 47,respectively.

[0222] As shown in FIG. 25, a barrier metal film 56 is formed in thethrough holes 51 to 55 and on the silicon oxide film 48. The barriermetal film 56 is an adhesion layer to increase the adhesion between theplugs to be formed in the holes 51 to 55 and the silicon oxide film 48.The film 56 is, for example, a titanium nitride film deposited bysputtering or CVD.

[0223] As shown in FIG. 26, a positive-type photoresist film 40 isformed on the barrier metal film 56 by means of spin-coating. Exposurelight is applied to the entire photoresist film 40 as is illustrated inFIG. 27. At this time, those parts of the photoresist film 40, whichexist outside the through holes 51 to 55 and near the rims thereof, areexposed to light. By contrast, the other parts provided deep in throughholes 51 to 55 are not thoroughly exposed to light.

[0224] Thereafter, as shown in FIG. 28, the photoresist film 40 isdeveloped, whereby those parts of the film 40, which have been exposedto light, are removed. The other parts of the film 40 remain in thethrough holes 51 to 55. Thereafter, as shown in FIG. 29, those parts ofthe barrier metal film 56, which lie outside the through holes 51 to 55,are removed by means of dry etching. The other parts of the barriermetal film 56 remain in the through holes 51 to 55, because they arecovered with the photoresist film 40. The barrier metal film 56 isetched at a rate much higher than the rate at which the photoresist film40 is etched. This prevents those parts of the film 56, which arecovered with the photoresist films 30 provided in the holes 51 to 55,from being exposed and etched away.

[0225] Then, as shown in FIG. 30, the photoresist film 30 provided inthe holes, 51 to 55 are removed by means of zone, ashing or the like. Asshown in FIG. 31, tungsten films 57 are grown on the barrier metal films56 provided in the through holes 51 to 55, filling the through holes 51to 55, by means of selective CVD or the like. The tungsten films 57 willbe processed into plugs, which electrically connect the first-layerwires 41, 43, 44, 46 and 47 to the second-layer wires which are to beformed on the silicon oxide film 48 in the next manufacturing step.

[0226] As shown in FIG. 32, the parts of the tungsten film 57 whichprotrude from the through holes 51 to 55 are removed by dry etching (orchemical mechanical polishing), whereby each tungsten film 57 has itsupper surface at the same level as the silicon oxide film 48.Thereafter, as shown in FIG. 33, the second-layer wires 61 to 64 areformed on the silicon oxide film 48. Specifically, the tungsten film isdeposited on the silicon oxide film 48 by sputtering and patterned bydry etching using a photoresist film as a mask.

[0227] (Embodiment 4)

[0228] Another method of forming plugs, which is Embodiment 4 of thisinvention, will be explained, by describing the sequence ofmanufacturing steps, with reference to FIGS. 34 to 39.

[0229] First, as shown in FIG. 34, first-layer wires 41 to 47 are formedabove an n-channel MISFET Qn and a p-channel MISFET Qp in the same wayas in the above Embodiment 3. Further, a silicon oxide film 48 isdeposited to cover the first-layer wires 41 to 47. Thereafter, thesilicon oxide film 48 is subjected to dry etching, thereby makingthrough holes 51 to 55 in the silicon oxide film 48.

[0230] Next, as shown in FIG. 35, a barrier metal film 56 is formed inthe through holes 51 to 55 and on the silicon oxide film 48. The barriermetal film 56 will be processed into adhesive layers. Thereafter, apositive-type photoresist film 40 is formed above the barrier metal film56 by means of spin coating. At this time, those parts of thephotoresist film 40, which exist outside the through holes 51 to 55 andnear the rims thereof, are exposed to light. By contrast, the otherparts provided deep in through holes 51 to 55 are not thoroughly exposedto light.

[0231] Further, the photoresist film 40 is developed, whereby thoseparts of the film 40 which have been exposed to light are removed, whileleaving the other parts of the film 40 in the through holes 51 to 55.Thereafter, as shown in FIG. 36, those parts of the barrier metal film56 which are not covered with the photoresist film 40 are removed bymeans of dry etching. Those parts of the photoresist film 40, whichremain in the through holes 51 to 55, are removed by means of zoneashing or the like.

[0232] As shown in FIG. 37, a shield layer 65 is formed in the throughholes 51 to 55 and on the silicon oxide film 48: The shield layer 65 isprovided as an under layer for the plugs that will be formed in thethrough holes 51 to 55 in the next manufacturing step. It is formed bydepositing copper (Cu) by, for example, sputtering.

[0233] Then, as shown in FIG. 38, a copper film 66 is deposited abovethe surface of the shield layer 65 by means of electroless plating orvapor deposition. Thereafter, as shown in FIG. 39, those parts of thecopper film 66 and the shield layer 65, which lie outside the throughholes 51 to 55, are removed by chemical mechanical polishing. Plugs 66Ato 66E, each composed of a copper film 66 and a shield layer 65, arethereby formed in the through holes 51 to 55.

[0234] Copper tends to diffuse into silicon oxide films and cannotfirmly adhere to silicon oxide films. Therefore, it is generallynecessary to provide a barrier metal film between a copper film and asilicon oxide film, in order to form copper plugs or copper wires in thethrough holes made in the silicon oxide film. The barrier metal filmshould be, for example, a titanium nitride film, which inhibitsdiffusion of copper and firmly adheres to the silicon oxide film.

[0235] In forming copper plugs or copper wires by means of chemicalmechanical polishing, it is therefore necessary to polish and remove thecopper film or copper shield layer from those parts of the silicon oxidefilm which lie outside trenches or through holes. Further, it is alsonecessary to polish and remove the barrier metal film provided beneaththe copper film or copper shield layer. Obviously, the chemicalmechanical polishing is inevitably complicated.

[0236] In the method of forming copper plugs according to the presentembodiment, those parts of the barrier metal film 56 which lie outsidethe through holes 51 to 55 are removed by dry etching before thechemical mechanical polishing is carried out. Thereafter, those parts ofthe copper film 66 and the shield layer 65 made of copper, too, whichlie outside the through holes 51 to 55, are polished and removed. Hence,the chemical mechanical polishing is simple in the present embodiment.The barrier metal film that prevents diffusion of copper may be made ofmaterial other than titanium nitride. It can be a tantalum nitride (TaN)film, a tungsten nitride (WN) film or the like.

[0237] (Embodiment 5)

[0238] A method of forming copper wires, which is Embodiment 5 of thepresent invention, will be explained, by describing the sequence ofmanufacturing steps, with reference to FIGS. 40 to 49. In this method,copper wires are buried in dual-damascene fashion.

[0239] First, as shown in FIG. 40, an n-channel MISFET Qn and ap-channel MISFET Qp are made in the same way as in the above Embodiments3 and 4. Then, first-layer wires 41 to 47 are formed above the n-channelMISFET Qn and the p-channel MISFET Qp. As shown in FIG. 41, a siliconoxide film 68 is deposited by CVD, to cover the first-layer wires 41 to47.

[0240] Next, as shown in FIG. 42, the silicon oxide film 68 is subjectedto dry etching using a photoresist film (not shown), thereby makingthrough holes 71 to 75 in the silicon oxide film 68 above the wires 41,43, 44, 46 and 47. Thereafter, as shown in FIG. 43, a positive-typephotoresist film 50 is formed in the through holes 71 to 75 and abovethe silicon oxide film 68 by means of spin coating.

[0241] As FIG. 44 shows, exposure light is applied to selected parts ofthe positive-type photoresist film 50, through a photomask 49. At thistime, those parts of the photoresist film 50, which exist outside thethrough holes 71 to 75 and near the rims thereof, are exposed to light.By contrast, the other parts provided deep in through holes 71 to 75 arenot thoroughly exposed to light.

[0242] Then, as shown in FIG. 45, the photoresist film 50 is developed,whereby those parts of the film 50 which have been exposed to light areremoved, while leaving the other parts of the film 50, not exposed tolight, in the through holes 71 to 75. The parts of the photoresist film50, thus left, fill the lower halves of the through holes 70 to 75.

[0243] As shown in FIG. 46, those parts of the silicon oxide film 68,which lie in wire-forming regions, are removed by dry etching using thephotoresist film 50 as a mask. Wire trenches 76 to 79 are thereby formedin the silicon oxide film 68. The silicon oxide film 68 is etched at arate much higher than the rate at which the photoresist film 50 may beetched. Hence, the etching of the film 68 stops at the time thephotoresist film 50 in each through hole is exposed at the bottom of thewire trenches 76 to 79.

[0244] As is shown in FIG. 47, the photoresist films 50 remaining in thethrough holes 71 to 75 are removed by means of ashing or the like. Then,as shown in FIG. 48, a barrier metal film 56, which will serve as anadhesive layer, is formed in the wire trenches 76 to 79 and in thethrough. holes 71 to 75 located below the wire trenches 76 to 79.Thereafter, a copper film 86 is deposited above the barrier metal film56. The barrier metal film 56 is a titanium film deposited by, forexample, CVD. The copper film 86 is deposited by means of sputtering orthe like.

[0245] Further, as shown in FIG. 49, those parts of the copper film 86which lie outside the wire trenches 76 to 79, and those parts of thebarrier metal film 56, which lie outside the trenches 76 to 79, areremoved by means of chemical mechanical polishing. Buried copper wires86A to 86D are thereby formed such that each is in one wire trench andone through hole is located below each wire trench.

[0246] In a dual-damascene process, wires trenches and through holes aremade in a silicon oxide film and wires are simultaneously buried in thewire trenches and the through holes located below the trenches. To makethe trenches and through the holes, an insulating film (e.g., a siliconnitride film) serving as an etching stopper is formed at the interfacebetween the trenches and the through holes. The level where theinsulating film is provided determines the depth of the wire trenches.More specifically, the trenches are made in the following way.

[0247] At first, a first silicon nitride film is formed on a siliconoxide film. Then, a second silicon oxide film is deposited on thesilicon nitride film. Thereafter, dry etching is performed on the secondsilicon oxide film, the silicon nitride film and the second siliconoxide film, thereby making through holes in these films. Next, thesecond silicon oxide film is subjected to dry etching using the siliconnitride film as a mask. As a result, the wire trenches are made in thesecond silicon oxide film. The through holes remain in the siliconnitride film and the first silicon oxide film both of which are locatedbelow the second silicon oxide film.

[0248] The dual-damascene process is, however, complicated, because thethree insulating films (i.e., the first silicon oxide film, the siliconnitride film and the second silicon oxide film) must be formed in orderto form one layer of buried wires. Further, if copper wires a formed onthe insulating film and one of the insulating films contains siliconnitride having a larger dielectric constant than silicon oxide film, theparasitic capacitance of the insulating films will increase.

[0249] By contrast, in the present embodiment, the wire trenches 76 to79 are made by utilizing the photoresist films buried in the throughholes 71 to 75 as etching stoppers. The through holes 71 to 75 and thewire trenches 76 to 79 are made in a single silicon oxide film 68. Thisshortens the time required to perform the dual-damascene process. Inaddition, the parasitic capacitance of the copper buried wires 86A to86E decreases because an insulating film (i.e., silicon nitride film)with a large dielectric constant s not used as an etching stopper.

[0250] (Embodiment 6)

[0251] A method of making self-aligned contact holes, which isEmbodiment 6 of the invention, will be explained, by describing thesequence of manufacturing steps, with reference to FIGS. 50 to 58.

[0252] First, as FIG. 50 shows, a p-type well 3 and an n-type well 4 areformed in the major surface of a substrate 1. Element-isolating trenches2 are made in the surfaces of the wells 3 and 4. A gate insulating film6 is formed in the trenches 2 and on the wells 3 and 4. Silicon oxidefilms 5 are formed, to fill the trenches 2. Thereafter, gate electrodes7 are formed in the following manner. For example, a polycrystallinesilicon film doped with n-type impurities such as phosphorus isdeposited on the substrate 1 by CVD. Then, a tungsten nitride film isdeposited on the polycrystalline silicon film by sputtering. Further, atungsten film is also deposited on the tungsten nitride film bysputtering. A silicon nitride film 8 is deposited on the tungsten filmby means of CVD. Thereafter, the polycrystalline silicon film, thetungsten nitride film, the tungsten film and the silicon nitride filmare patterned by dry etching using a photoresist film as a mask. Eachsilicon nitride film 8 on one gate electrode 7 is an insulating filmthat is required to form a contact hole (later described) inself-alignment with the gate electrode 7.

[0253] Next, as shown in FIG. 51, n-type impurities such as phosphorusare ion-implanted into the p-type well 3, forming n⁻-type semiconductorregions 9. Into the n-type well region 4, p-type impurities (boron) areion-implanted, thus forming p⁻-type semiconductor regions 20. Then, asilicon nitride film 27 is deposited by CVD to cover the gate electrodes7. Further, a silicon oxide film 11 is deposited on the silicon oxidefilm 27. The silicon oxide film 11 is subjected to chemical mechanicalpolishing to attain a flat surface. The silicon nitride film 27 is aninsulating film required to make contact holes (later described) inself-alignment with the element-isolating trenches 2.

[0254] In order to make contact holes in self-alignment with the gateelectrodes 7 and the element-isolating trenches 2, the silicon nitridefilms 8 are provided on the gate electrodes 7, respectively, and thesilicon nitride film 27 is provided, to close the element-isolatingtrenches 2. Thus, a single-layer film, i.e., the silicon nitride film27, covers the diffusion layers (i.e., the n⁻-type semiconductor regions9 and the p-type semiconductor regions 20), whereas a two-layer filmcomposed of the silicon nitride films 8 and 27 covers the gateelectrodes 7.

[0255] As shown in FIG. 52, the silicon oxide film 11 provided above thediffusion layers (n⁻-type semiconductor regions 9 and p⁻-typesemiconductor regions 20) is subjected to dry etching using aphotoresist film (not shown) as a mask. At the same time, those parts ofthe silicon oxide film 11 which lie above the gate electrodes 7 aredry-etched at a rate higher than the rate at which the silicon nitridefilm 27 may be etched. This prevents the silicon nitride film 27 lyingbeneath the silicon oxide film 11 from being removed.

[0256] If the silicon oxide film 11 is dry-etched by using the siliconnitride film 27 lying beneath the film 11 as a mask, a single-layerfilm, i.e., the silicon nitride film 27, will remain on the diffusionlayers (the n⁻-type semiconductor regions 9 and the p⁻-typesemiconductor regions 20), and a two-layer film composed of the siliconnitride films 8 and 27 will remain on each gate electrodes 7. Thesilicon oxide film 5, lying partly on the substrate 1 and partly in theelement-isolating trenches 2, will be etched excessively if the siliconnitride films 8 and 27 provided on each gate electrode 7 are dry-etchedin the next step, together with the silicon nitride film 27 provided onthe diffusion layers (the n⁻-type semiconductor regions 9 and thep⁻-type semiconductor regions 20), in order to make contact holes thatreach these diffusion layers. Consequently, the leakage current in eachelement will increase thereby deteriorating the characteristics of theelement. It is necessary to prevent excessive etching of the substrate 1and the silicon oxide film 5. To this end, the silicon nitride film 8that lies above each gate electrode 7 and that part of the siliconnitride film 27 which lies on the film 8 need to be etched in one step,and those parts of the silicon nitride film 27 which lie on thediffusion layers (n⁻-type semiconductor regions 9 and p⁻-typesemiconductor regions 20) needs to be etched in another step. Hence, itwould be necessary to use two photomasks.

[0257] Then, in the present embodiment, the silicon oxide film 11 isdry-etched by using the silicon nitride film 27, which lies beneath thesilicon oxide film 11, as etching stopper. Thereafter, as shown in FIG.53, a positive-type photoresist film 60 is spin-coated on the siliconoxide film 11. Exposure light is applied to the entire surface of thephotoresist film 60. At this time, those parts of the photoresist film60 which lie above the gate electrode 7 are thin and thereforethoroughly affected by the light. Those parts of the photoresist film 60which lie above the diffusion layers (the n⁻-type semiconductor regions9 and the p⁻-type semiconductor regions 20) are thick and affected bythe light at only the upper part.

[0258] Next, as shown in FIG. 54, the photoresist film 60 is developed,whereby those parts exposed to light are removed. At this time, thoseparts of the silicon nitride film 27, which lie above the gateelectrodes 7 and which are indicated by arrows, are thereby exposed. Onthe other hand, the other parts of the film 27, which lie on thediffusion layers (the n⁻-type semiconductor regions 9 and the p⁻-typesemiconductor regions 20), are not exposed. This is because the parts ofthe photoresist film 60, which have not been exposed to light, remainabove the diffusion layers.

[0259] As shown in FIG. 55, those parts of the silicon nitride film 27and 8, which lie above the gate electrode 7 is subjected to dry etchingusing, as a mask, the those parts of the photoresist film 60 which lieabove the diffusion layers (the n⁻-type semiconductor regions 9 and thep⁻-type semiconductor regions 20). The silicon nitride films 27 and 8are etched at a rate much higher than the rate at which the siliconoxide film 11 may be etched. Therefore, the etching is stopped at thetime when the silicon nitride film 8 (covering the gate electrode 7) isetched to almost the same thickness as that of the silicon nitride film27 covering the diffusion layers (i.e., the n⁻-type semiconductorregions 9 and the p⁻-type semiconductor regions 20).

[0260] As shown in FIG. 56, those parts of the photoresist film 60,which remain above the diffusion layers (the n⁻-type semiconductorregions 9 and the p⁻-type semiconductor regions 20), are removed bymeans of ozone ashing. Then, as shown in FIG. 57, those parts of thesilicon nitride films 27 which covers the diffusion layers (the n⁻-typesemiconductor regions 9 and the p⁻-type semiconductor regions 20) areremoved by dry etching. And, that part of the silicon nitride film 8which covers the gate electrode 7 is also removed by dry etching. As aresult, contact holes 91 and 92 are thereby made, thereby exposing then⁻-type semiconductor regions 9, and contact holes 93 and 94 are madethereby exposing the p⁻-type semiconductor regions 20, and a contacthole 95 is made thereby exposing the gate electrode 7. The siliconnitride films 8 and 27 are subjected to anisotropic etching, therebyleaving silicon nitride films 27 on the sides of every gate electrode 7.

[0261] The silicon nitride film 8 and 27 are etched after those parts ofthese films which lie above the diffusion layers (the n⁻-typesemiconductor regions 9 and the p⁻-type semiconductor regions 20), andthe gate electrode 7 have been etched to almost the same thickness.Hence the silicon oxide film 5 provided in the element-isolatingtrenches 2 or the substrate 1 would not be etched excessively even ifthe silicon nitride films 8 and 27 were etched at the same time.

[0262] In Embodiment 6, the contact hole 95, exposing the gate electrode7 can be made at the same time the contact holes 91 to 94 are made inself-alignment with respect to the other gate electrodes 7 and theelement-isolating trenches 2. Therefore, it suffices to use only onephotomask to make the contact holes 91 to 95.

[0263] Next, as shown in FIG. 58, n-type impurities (phosphorus orarsenic) are ion-implanted into the p-type well 3 through the contactholes 91 and 92, thereby forming n⁺-type semiconductor regions (sourceand drain) 31, whereby n-channel MISFETs Qn are formed. Further, p-typeimpurities (boron) are ion-implanted into the n-type well 4 through thecontact holes 93 and 94, thereby forming p⁺-type semiconductor regions(source and drain) 32, whereby p-channel MISFETs Qp are formed.Thereafter, first-layer wires 41 to 47 are formed on the silicon oxidefilm 11 in the same way as in Embodiments 3 to 5.

[0264] The invention has been described, with reference to someembodiments. The present invention is not limited to these embodiments.Rather, various changes and modification can be made without departingthe spirit and scope of the invention.

[0265] Some of the various advantages achieved by this invention are asfollows:

[0266] (1) The invention enhances the reliability and manufacturingyield of a DRAM having data-storing capacitive elements, each having itslower electrode formed in a trench made in an insulating film.

[0267] (2) The invention makes it possible to form, with a high yield,conductive layers in the trenches Or through holes made in an insulatingfilm.

[0268] (3) The invention renders it possible to form conductive layersin the trenches or through holes made in an insulating film, byperforming few manufacturing steps.

What is claimed is:
 1. A method of manufacturing a semiconductorintegrated circuit device, comprising the steps of: (a) forming a firstconductive film on a major surface of a semiconductor substrate, forminga first insulating film on the first conductive film, and making atrench or a through hole in the first insulating film; (b) forming asecond conductive film in the trench or the through hole and on thefirst insulating film, said second conductive film extending through thetrench or the though hole and electrically connected to the firstconductive film; (c) covering the second conductive film with aphotoresist film and applying exposure light to the photoresist film,thereby exposing to light at least that part of the photoresist filmwhich lies outside the trench or the though hole; (d) removing that partof the photoresist film which is exposed to light, thus leaving theother, unexposed part of the photoresist film in the trench or thethrough hole; and (e) removing that part of the second conductive filmwhich is not covered with the photoresist film, thereby leaving theother part of the second conductive film in the trench or the throughhole.
 2. The method of manufacturing a semiconductor integrated circuitdevice according to claim 1, wherein the second conductive film isremoved in part in the step (e) etching method.
 3. The method ofmanufacturing a semiconductor integrated circuit device according toclaim 1, wherein the second conductive film is removed in part in thestep (e) by chemical mechanical polishing method.
 4. The method ofmanufacturing a semiconductor integrated circuit device according toclaim 1, wherein the photoresist film is removed in part in the step (d)by developing the photoresist film.
 5. The method of manufacturing asemiconductor integrated circuit device according to claim 1, after thestep (e) has been performed, further comprising a step (f) of removingthat part of the photoresist film lying in the trench or the throughhole and selectively growing a third conductive film on the secondconductive film exposed in the trench or the through hole, therebyburying the third conductive film in the trench or the through hole. 6.The method of manufacturing a semiconductor integrated circuit deviceaccording to claim 5, wherein the second conductive film is made oftitanium nitride or tungsten.
 7. The method of manufacturing asemiconductor integrated circuit device according to claim 5, whereinthe third conductive film is made of tungsten or aluminum alloy.
 8. Themethod of manufacturing a semiconductor integrated circuit deviceaccording to claim 5, after a step (f) has been performed, furthercomprising the step (h) of forming a fourth conductive film on the firstinsulating film and electrically connecting the fourth conductive filmto the first conductive film via the third conductive film in the trenchor the through hole.
 9. The method of manufacturing a semiconductorintegrated circuit device according to claim 1, further comprising thefollowing steps (f) and (g) which are performed after the step (e); (f)removing that part of the photoresist film which lie in the trench orthe through hole, and forming a fifth conductive film in the trench orthe through hole and on the first insulating film; and (g) growing asixth conductive film on the fifth conductive film and removing thoseparts of the sixth and fifth conductive films which lie outside thetrench or the through hole, thereby leaving the sixth and fifthconductive films in the trench or the through hole.
 10. The method ofmanufacturing a semiconductor integrated circuit device according toclaim 9, wherein the second conductive film is made of titanium nitrideor tantalum nitride.
 11. The method of manufacturing a semiconductorintegrated circuit device according to claim 9, wherein the fifth andsixth conductive films are made of copper.
 12. The method ofmanufacturing a semiconductor integrated circuit device according toclaim 9, wherein said parts of the sixth and fifth conductive films areremoved by chemical mechanical polishing method.